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Consider the MIPS code: addi $ 2 , $ 0 , 0 L : l w $ 3 , 0 ( $ 8 ) B

Consider the MIPS code:
addi $2,$0,0
L: lw $3,0($8)
B1: beg $3,$16,L1
lw $4,0($9)
sw $4,8($8)
sub $5,$3,$4
lw $7,4($8)
B2: bne $7,$17,L2
addi $2,$2,1
sw $2,4($9)
L2: addi $3,$5,-1
sw $3,0($8)
Iw $6,8($9)
L1: lw $9,12($9)
B3: beg $9,$0,L3
sub $16,$6,$16
addi $8,$8,12
B: jL
L3: sub $16,$16,$2
sw $16,0($10)
which is loaded into memory, with the first instruction at location 041008b00, to be executed in the
above DPU. Before running the code, assume that the FC registers of interest contain the following values:
$3: 0xffffffff
$4: 0x0
$5: 0x0f7a
$6: 0288
$7: 01
$8: 0x1003ab00
$9: 0x10088b00
$10: 0x1008cb00
$16: 0x3
$17: 0x0
and the memory locations referenced by the code contain:
mem[0x1003ab00]: 0x1
mem[0x1003ab04]: 0x0
mem[0x1003ab08]: 0x7
mem[0x1003ab0c]: 0x2
mem[0x1003ab10]: 0x11
mem[0x1003ab14]: 0x3
mem[0x1003ab18]: 0x1
mem[0x1003ab1c]: 0xa
mem[0x1003ab20]: 0x2b
mem[0x10088b00]: 0xffffffc
mem[0x10088b04]: 0x2a
mem[0x10088b08]: 0x5
mem[0x10088b0c]: 0x10088b24
mem[0x10088b24]: 0x0
mem[0x10088b28]: Oxe
mem[0x10088b2c]: 0xffffffff
mem[0x10088b30]: 0x10089b00
mem[0x10089b00]: 0x2
mem[0x10089b04]: 0x1d
mem[0x10089b08]: 0x1
mem[0x10089b0c]: 0x0
mem[0x1008cb00]: 0x0DPU Show how the code is executed in the DPU of the image, as follows:
A. Give the single timing diagram resulting from the run, based on the register and memory values listed
above.
B. Provide all values generated within the DPU, either as data or control signals, separately for each
machine cycle, from the recall phase of the first instruction, to the result storage phase of the last
instruction.
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