Consider the multiplier design using an AND array with a Log-time Tree, as shown on page 37/80 (see also pages 20-23). How many gates are contained within the AND array of a (16-bit * 16-bit) multiplier using this design? 32 two-input AND gates 64 two-input AND gates 128 two-input AND gates 256 two-input AND gates 512 two-input AND gates 1024 two-input AND gates Cost/performance tradeoff, can be pipelined: Several multiplication performed in parallel