Consider the periodic input signal with a period of 10ns as described in the 1 period window. CLK ^^^^^^^^^^^ Signal IN t (ns) 0 1 2 3 4 5 6 7 8 9 10 a) Above signal IN is given to the following circuitry driving the 50fF output capacitance. How much dynamic power is drawn while applying above 10 ns input? Assume the supply voltage is 1 V. You may assume that the NOR gate does not have any internal delay. (15 points) IN Ons b) From the above problem, we found that there was a buffer (two inverters) for the lower input port as below. We also found that each inverter causes a delay of 0.75ns. All the logic gates output rising and falling time is only 50ps. Please calculate the dynamic power with new setups. (15 points) IN 0.75ns IN OUT 50fF Ons OUT 50fF