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Consider the single-cycle datapath shown on the next page. We would like to implement the jump-register (jr) instruction in this datapath. jr rs This instruction
Consider the single-cycle datapath shown on the next page. We would like to implement the jump-register (jr) instruction in this datapath. jr rs This instruction changes the value of the PC to be equal to the contents of the rs register. a) Do you need to modify the single-cycle datapath (given on the next page) in order to support the execution of this instruction? If so, describe (in words) the major changes you would make to the datapath. You are allowed to insert wires, buses, adders, mux, new control signals, or any other block. Draw a neat figure (either by modifying the figure on the next page or on a separate sheet) to show your changes. (10 points) b) Fill out the table for the control signals for this instruction. If you have added new control signals, add new columns for those to the table. Put a "don't care." for signals that are (5 points) RegDst ALUOp ALU PCSrc Mem MemReg MemtoR Src (Branch) Read Write Write eg Consider the single-cycle datapath shown on the next page. We would like to implement the jump-register (jr) instruction in this datapath. jr rs This instruction changes the value of the PC to be equal to the contents of the rs register. a) Do you need to modify the single-cycle datapath (given on the next page) in order to support the execution of this instruction? If so, describe (in words) the major changes you would make to the datapath. You are allowed to insert wires, buses, adders, mux, new control signals, or any other block. Draw a neat figure (either by modifying the figure on the next page or on a separate sheet) to show your changes. (10 points) b) Fill out the table for the control signals for this instruction. If you have added new control signals, add new columns for those to the table. Put a "don't care." for signals that are (5 points) RegDst ALUOp ALU PCSrc Mem MemReg MemtoR Src (Branch) Read Write Write eg
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