Consider the variable$-$stage pipelined processor with two execution units and pipelined caches, as shown below. Instruction fetch is a two$-$stage process followed by decode where registers are also read in the second half of the cycle. Additionally, the pipeline consists of a separate execution unit for floating point $($FP$)$ operations. The single stage first execution unit is for all Integer Arithmetic Branch operations $($excluding integer multiply$)$ The two$-$stage second execution unit is for floating point $($FP$)$ Add$/$Sub and Multiply $($both integer and FF$)$ operations. The data cache is pipelined and takes two stages for read$/$write operations $($including integer and FP loads and stores$).$ The final stage performs registers writes in the first half of the cycle, if any.

CLO$-1,$ C$3$ Application, PLO$-2$ Problem Analysis$)$

r the clock cycle time for the above pipeline to be $250$ ps and assume cach stage takes equaltime

a$)$ Calculate the latency of integer multiply instruction, For the mentioned pipeline Branch Target Address can be known by the third cycle and branch condition by the end of EX stage. Determine the reduction in CPI for a program having $20\%$ conditional branches and $5\%$ unconditional branches if the branch condition in also evaluated earlier in the decode stage. Assume freezz'stall pipeline strategy is implemented

c$)$ Defermine how many minimum stall cycles are required between a load instruction and the different classes of instructions that use the load's result during the execution stage. For a program, assume $30\%$ of the code consist of FP ADD instruction followed immediately by another dependent FP ADD instruction. What is the addition to the CPI due to these instructions assuming partial results cannot be forwarded? What type of hazard would this be$?$

Considering that branch conditions are now evaluated in the decode stage as discussed in part$-$b$),$ what effect will this change have on the program's CPI if $12\%$ branch instructiom