Consider the Verilog module shown below: module rand_num (input logic clk, rst, load, input logic [7:0] seed, output logic [7:0] val); always ff (posedge clk) begin if (rst) val8'b0; else if (load) valseed; else val[val[5] A val[2],val[7:1]1; end endmodule How many input signals are specified? Select one: a.6 b.5 Oc.3 O e.4