Consider this code, which has a RAW hazard:

$($a$)$ When we can add data forwarding hardware in the system, is any stalling required for this

combination? If so: how many cycles of stalling are required, and what Boolean expression is

needed in the pipeline interlock logic to detect the need to stall $($in the first cycle, if multiple stalls

are needed$)?$

$($b$)$ What data forwarding hardware must be added to the variation $1$ MIPS to provide data to the second

instruction without stalling? Show the required hardware by drawing it in a different color on a

diagram of the variation $1$ MIPS pipeline. $($You do not have to include all the details of the standard

pipeline, but give enough to see how the new hardware fits in$.)$

$($c$)$ The data is being forwarded from where to where, and replacing what? Also, what Boolean

expression can be used to decide whether to activate the path that forwards the data in a given clock

cycle?