Consider two caches: a) a 32 KB instruction cache with a 32 KB data cache, and b) a 64 KB unified cache. Assume a hit takes 1 cycle and the miss penalty is 60 clock cycles for both caches.

Which of the caches has the lower miss rate? The miss rate of the caches can be calculated from the numbers in Figure B.6 on page B-15. Assuming 20% of the instructions are data transfer instructions. Note that every instruction has to be fetched from the cache. Pay attention to the method of calculating the miss rate for the split cache in the example.

What is the average memory access time of each cache? Note that the unified cache has structural hazards. A load or store hit takes 1 extra cycle on a unified cache because one cache port cannot satisfy two simultaneous requests. You do not need to differentiate read and write operations to data cache.

Unified Instruction cache Size (KB) Data cache cache 63.0 8.16 44.0 40.9 3.82 51.0 16 1.36 38.4 32 43.3 0.61 39.4 36.9 0.30 35.3 128 36.2 256 0.02 32.6 32.9 Figure B.6 Miss per 1000 instructions for instruction, data, and unified caches of dif- ferent sizes. The percentage of instruction references is about 74%. The data are for two-way associative caches with 64-byte blocks for the same computer and bench- marks as Figure B.4. Unified Instruction cache Size (KB) Data cache cache 63.0 8.16 44.0 40.9 3.82 51.0 16 1.36 38.4 32 43.3 0.61 39.4 36.9 0.30 35.3 128 36.2 256 0.02 32.6 32.9 Figure B.6 Miss per 1000 instructions for instruction, data, and unified caches of dif- ferent sizes. The percentage of instruction references is about 74%. The data are for two-way associative caches with 64-byte blocks for the same computer and bench- marks as Figure B.4