Convolutional Neural Networks $($CNNs$)$ are special type of Deep Neural Networks $($DNNs$).$ This kind of neural networks are widely applied to image processing tasks. Unlike traditional Artificial Neural Networks $($ANNs$),$ CNNs are able to process $3-$dimensional input data directly.

Due to the fact of the data$-$flow driven nature, parallel computing is highly beneficial to decrease the execution time of CNNs$.$ Nowadays, the training of DNNs is done with the help of Graphical Processing Units $($GPUs$).$ GPUs offer a highly powerful platform with many processing elements, which are programmable with the help of high$-$level languages such as CUDA or OpenCL. Moreover, frameworks like Caffe further simplify the utilization of GPUs for machine learning applications. However, the advantage in energy efficiency of Field Programmable Gate Arrays $($FPGAs$)$ in comparison to GPUs is well known. Furthermore, researchers have found out that DNN implementations on FPGAs can outperform their counterpart implementation on GPUs without using batch processing. The energy consumption of the platform is a critical aspect, especially if the target device is mobile and$/$or the machine learning application cannot be processed on server platforms due to safety constraints. For such applications, like autonomous driving, FPGA or Application Specific Integrated Circuits $($ASICs$),$ such as coprocessors, need to be considered.

In this assignment, you need to work on finding ways for accelerating CNNs on FPGAs using hardware$/$software codesign implementation, and a corresponding design flow exploiting FPGAs' Dynamic Partial Reconfiguration $($DPR$)$ capabilities.