could you help me solve question 3a,b and c?

And show me how to solve thank you.

EXERCISE 3 Consider the following VHDL code library ieee; use ieee.std_logic_1164.all; entity comb_cir is port (A: in stdlogic; B in std_logic; C: in std_logic; x : out std_logic; Y: out std_logic); end comb_cir; architecture arch of comb cir is begin X