Course Objective: Design a Complete CPU System

The course objective is to design a complete CPU system, starting with learning about ISA, advanced ALU, datapath and control, and pipelining in theory. To make this learning more effective, a step$-$by$-$step design of the complete CPU system will be carried out through pen and paper, simulation tools, hardware, etc.

Task: Design a $32-$bit Single$-$Cycle CPU

Design a new $32-$bit single$-$cycle CPU with separate Data and Instruction Memory. The ISA should be general$-$purpose enough to run provided general programs:

IN & OUT: Perform input$/$output operations.

Benchmark Programs.

Focus your ISA design on the following three categories of programs:

Simple arithmetic & logic operations.

Programs that require checking conditions.

Loop type programs.

Assembler for ISA

In this project, you will use an assembler for your ISA. The assembler reads a program written in assembly language from a text file $(.$asm or $.$s$),$ translates it into binary code, and generates an output file $(.$txt or $.$bin$)$ containing machine code. These generated output files will be useful when developing the actual CPU in Verilog.

Language: You can use any high$-$level language.

I$/$O Format:

The input code will be written in a text file $($e$.$g$.,$ extension bin$)$ in assembly format following your ISA.

There will be one instruction per line.

The output will be generated in binary or hexadecimal format, which will later be transferred into the RAM block of the Verilog model.

Title: CPU Type: Verilog

In this part of the project, you will design a Datapath and Control path of your proposed $32-$bit architecture. The Datapath must have all the necessary components, which must be adequately connected.

Complete Hardware Based on $32-$bit ISA:

Students will design hardware parts such as the ALU, Register Files, Memory, and Control Unit and connect them.

There will be a few simulation labs throughout the semester that have ModelSim installed. The work in these simulation labs will help in completing this part.

Sample Verilog files of Register File, ALU, etc., are provided. You can use them and make modifications based on your own ISA. However, you must add JAL and JR instructions to the model.