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cross couples NOR - automatically ime negation QN ( t + At ) of Q 0 0 reset ! 1 1 Figure I. Part 1

cross couples NOR -automatically ime negation QN(t + At) of Q 00 reset !11 Figure I. Part 1 Quartus Schematic gaH Inputs Outputs S alto, Rg(t) Sg(t) Q(0) Q(t + At)0001 hold o o QCV)00110 set o 101100011101000110101110 X X 111 X X Table 1. Truth Table for cross-coupled NOR gates Figure 1 is the complete schematic we did for the first part of the lab. The logic was already done for us so designing it was mostly following the diagram on the lab handout using the previous skills we learned from the previous labs. The final product is a gated RS latch that uses cross-coupled NOR gates. Table 1 is the truth table for the schematic and we had to ignore the case were Sg(t)=Rg(t)=1 since this is the invalid state which would make the circuit unstable due to the nature of cross coupled NOR gates. All testing was done on the programmed DE 10 board and toggling the switches and making sure the outputs on LEDR lights made sense. Figure 1 depicts a gated RS latch circuit. AND2 SW[0] NORD Ro Q LEDR[0 inst inst2 SWOJ CLK NORD ANDZ ON OUTPUT LEDR[1] SW[2] inst3 inst1 Figure 1. A gated RS latch circuit Q1. When the CLK (SW[O]) is high, does the output change when R and S are changed? If so, give examples. Q2. When the CLK is low, does the output change when R and S are changed? If so, give examples. Q3. Is there any case when Q = QN?(i.e. when LEDR[1] and LEDR[0] are either both ON or both OFF). Describe this case. Since Q and QN should always be complements, this case would be an illegal state for an RS latch. Q4. When R=S=0, what happens to the output when the CLK is toggled? Q5. When R=S=1 and CLK goes from 1 to 0, what happens to the output? Explain why this happens. Is it what you expect?

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