(d) Calculate the number of cycles it takes to execute the code segment on Machine I and Machine II.

2 Pipelining (II) Consider two pipelined machines implementing MIPS ISA, Machine I and Machine II: Both machines have the following five pipeline stages (very similarly to the basic 5-stage pipelined MIPS processor we discussed in lectures), and one ALU: 1. Fetch (one clock cycle) 2. Decode (one clock cycle) 3. Execute one clock cycle) 4. Memory (one clock cycle) 5. Write-back (one clock cycle). Machine I does not implement interlocking in hardware. It assumes all instructions are independent and relies on the compiler to order instructions such that there is sufficient distance between dependent instructions. The compiler either moves other independent instructions between two dependent instruc- tions, if it can find such instructions, or otherwise, inserts nops. Assume internal register file forwarding (an instruction writes into a register in the first half of a cycle and another instruction can correctly access the same register in the next half of the cycle). Assume that the processor predicts all branches as always-taken. Machine II implements data forwarding in hardware. On detection of a flow dependence, it forwards an operand from the memory stage or from the write-back stage to the execute stage. The load instruction (1w) can only be forwarded from the write-back stage because data becomes available in the memory stage but not in the execute stage like for the other instructions. Assume internal register file forwarding (an instruction writes into a register in the first half of a cycle and another instruction can access the same register in the next half of the cycle). The compiler does not reorder instructions. Assume that the processor predicts all branches as always-taken. Consider the following code segment: Copy: lw $2, 100($5) $2, 200($6) addi $1, $1, 1 bne $1, $25, Copy Initially, $5 0, $6 = 0, $1 0, and $25 25. SW