D Use the following Verilog module to draw the output waveforms for the specified inputs, where $y1,$ and $y2$ are initially $0.(6\%$

module my$\_$unit$($clk$,($:$x,y1,y^2\}$;

input clk$,x$;

output $y_1,y^2$;

reg $y1,y2$;

wire $w$;

assign $w=x|y1|$;

always@$($posedge clk$)$

y w;

always@$($negedge clk$)$

$y1y^2$;

endmodule