Data Format: As described in Homework assignment 4, the input data for our logic simulator will look like this:

-- this is a comment gate a xor 6.7 gate b threshold 1 3.6 -- so is this wire a 3.2 b -- blank lines (like the above) are allowed wire b 1.5 a 1.8 a gate c xor 1.5 

Each gate or wire description must begin on a new line, optionally preceeded by white space. Comments extend to the end of line and, if present, must either occupy an entire line or must begin after the end of the gate or wire description.

Gate names must begin with a letter, which may be followed by any number of letters or numbers.

There are 4 kinds of gates:

• xor gatesgate x xor 1.0

  Xor gates have a single attribute in the description, the delay. The delay must be a positive nonzero floating point number.

• threshold gatesgate x threshold 2 1.0

  Threshold gates have two attributes in the description, the threshold, an integer, and a delay. The threshold must be non-negative. The delay must be a positive nonzero floating point number.

• input gatesgate x input 1 1.0 0

  Input gates have three attributes the initial value, shown as 1 above, the delay, shown as 1.0 above, and the number of times it changes, shown as 0 above. The initial value must be 1 (for true) or 0 (for false). The delay must be a positive nonzero floating point number. The change count must be a non negative integer.

• output gatesgate x output

  Output gates have no additional attributes.

Wires are specified as for Machine Problem 2, with a single source gate and one or more destinations, with a positive nonzero delay before the name of the destination gate.

While or after the circuit description is read in in order to build a data structure, your program must check certain sanity constraints. In writing your code, we recommend that you get it working before worrying about these checking these sanity constraints:

• Input gates may not be destinations of any wires.
• Output gates may not be sources for any wires.
• Xor gates must be the destination of exactly 2 wires.
• If a threshold gate is the destination of n wires, it may not have a threshold greater than n.

Your program must read the entire circuit description presented to it, and then output as much of the circuit as it is able to understand, in a format substantially similar to the input format. The purpose of this output is to verify that your program has indeed understood that part of the input.

Where a gate or wire is partially defective, your program may include parts of that gate or wire in the output.

Multiple destination wires may be output as a series of similar wires, all gates may be output before all wires, and comments should not be output. The purpose of this rule is to elminiate the need to preserve irrelevant information.

Where your program is unable to process the input, it should give meaningful error messages.

Your program must exit reporting success if no errors in the input were encountered, and exit reporting failure if any errors were detected (but only after outputting that part of the input that it was able to understand).

Your program must not have any unhandled exception, regardless of the input.

Additionally, your program must be written in clearly commented and legible Java, conforming to the Java style and documentation guidelines we have been using.

Make sure that the file you submit is called MP3.java, with a header comment saying MP3.java, where the next line is an author comment, as in MP1, giving your name, formatted as in University records and your discussion section number.

For each class you alter or create, there must be a Javadoc comment giving the author(s) and the version (use the date of the last modification), again, as in MP1. And, all public fields of each class should have Javadoc comments giving appropriate information (unless blindingly obvious).

Your code should pass the basic format tests when you use the command ~dwjones/format MP3.java

Your code should detect and complain about negative delays on wires.

Your code should detect and complain about wires that connect to undeclared gates.