Data Hazards

Consider the MIPS assembly language code segment given below.

I1: add $s1, $s2, $s3

I2: add $s2, $s1, $s4

I3: add $s1, $s1, $s2

The clock period for the MIPS pipelined processor is specified below for the processor with and without forwarding logic.

With Forwarding 150 psec

Without Forwarding 200 psec

(a) Identify the data dependencies and their type (i.e. RAW, WAR, and WAW). Use the following format: I2 I4, Register $t0, RAW To indicate a RAW data dependency between instructions I2 and I4, due to register $t0.

(b) Assume that there is NO forwarding logic in the processor. Identify the RAW data hazards. Use the following format: I2 I3, Register $t4 To indicate a data hazard between instructions I2 and I3, because of register $t4.

(c) Assume that there is forwarding logic in the processor. Identify the RAW data hazards.

(d) What is the total execution time (ET) of this code segment on the processor without forwarding logic and with forwarding logic? What is the speedup achieved by adding forwarding logic to a pipeline that did not have it?