Derive a minimal state table for a Moore model FSM that acts as a three-bit parity generator. For every three bits that are observed on the input z during three consecutive clock cycles, the FSM generates the parity bit T = 1 if and only if the number of 1s in the three-bit sequence is odd. Thus, this is an even parity generator.

Implement the circuit in Logisim. Note that this is not a sliding window. Once you take your three bits in, you reset and start looking at the next 3 bits.

Input Pins

z is your main input. You will also need the clock pin Clock. There is also an input named Enable. Hook this up to the enable pins on your flip flops.

Output Pins

T is your output, the parity bit.