Describe each level of cache present. What are the sizes and set associativity of each? For each level, tell how many bits are used of the address to determine the tag, index, and byte (assume all cache lines are 64 bytes). Total memory size: 16 GB

L1 Data Cache 2 x 48 KB (12-way, 64-byte line) + 8 x 32 KB (8-way, 64-byte line)

L1 Inst. Cache 2 x 32 KB (8-way, 64-byte line) + 8 x 64 KB (8-way, 64-byte line)

L2 Cache 2 x 1.25 MB (10-way, 64-byte line) + 2 x 2 MB (16-way, 64-byte line)

L3 Cache 12 MB (12-way, 64-byte line)