Description: Design a simplified version of a MIPS machine and write a Verilog program that describes its structure and simulates its functioning. Use gate-level modeling for all components unless otherwise specified. The machine should include the following components:

General purpose registers (register file): 4 registers, 16-bit long, numbered 0 - 3. Register $0 must contain 0 (read-only). Implemented in behavioral modeling.

Other registers: 16-bit program counter, pipeline registers. Implemented by reg vectors in Verilog.

Istruction Memory. Word size: 16 bits, word addressed, size: 1024 bytes. Implemented by reg array in Verilog.

Data Memory. Word size: 16 bits, byte addressed, size: 1024 bytes. Implemented by reg array in Verilog.

ALU: 16-bit data, 4-bit control. Functions: and, or, nor, nand, add, sub, slt, Zero. Implemented at gate-level.

Main Control unit: Behavioral model.

Branch Control unit: Gate-level model.

Other components necessary to connect the main components: multiplexes implemented at gate-level.

Instruction set

Instruction	Opcode
add	0000
sub	0001
and	0010
or	0011
nor	0100
nand	0101
slt	0110
addi	0111
lw	1000
sw	1001
beq	1010
bne	1011

Instruction format

R-format (add, sub, and, or, nor, nand, slt)

op	rs	rt	rd	unused
4	2	2	2	6

I-format (addi, lw, sw, beq, bne)

op	rs	rt	address / value
4	2	2	8

Extra credit (maximum 5 points). Implement one of the following: additional MIPS instructions (e.g. jump), improvements of the pipeline (forwarding or stalling), a data cache. For implementing the data cache see cache.vl, cache2.vl.

Testing: To test the MIPS machine write a simple program that includes arithmetic and logic (add, addi, sub, and, or, nor, nand, slt), data transfer (lw, sw) and branch (beq, bne) instructions. Use immediate arithmetic instruction (addi) to introduce numeric constants in your program. Include in your report:

The assembly source of the test program with comments explaining the algorithm.

The machine code (the contents of the memory)

Simulation results obtained by running the Verilog program. To monitor the execution of the test program for each instruction display the value at the write data input of the register file. For the branch instructions show results from both decisions (branch taken and branch not taken). Show the PC in the simulation output. For the pipelined processor show results with and without nop's that demonstarte the pipeline hazards.

Progress reports: Three progress reports and a final report describing the current status of the project and including the design of the major components of the MIPS machine should be submitted. Each report should be a single Word or PDF document and must include:

A detailed description of the instruction set architecture of the current version of the CPU (instruction codes, formats, meaning).

Logic diagrams or truth tables (for non-gate level designed modules) of the CPU and each of its major components (ALU, regfile, control unit, branch control). The diagrams and tables must use labels for all components and data/control signals corresponding exactly to the modules, input/outputs and wire names used in the Verilog code.

The Verilog source code including comment for each module defined or used.

The source and the machine language translation of the test program with comment showing the result that each instruction produces.

Test results showing the correct functioning of the CPU by running the test program.