Description

The purpose of the data unit is to read the words stored in the memory RAM and extract status signals such as the opcode, address, and flags listed below and send them to the control unit. In addition, it also executes the control signals received from the control unit such as register load, memory read$/$write$,$ and arithmetic, logic, and shift unit $($ALU$)$ operations. The Data Unit will send to the Control unit the status signals which include the machine instructions bits which have the $($opcode$,$ indirect bit, address bits, and the status flags $($Z$,$ I, N$,$ S$,$ K$,$ M$).$ ROM can be used to control memory. The Control Unit will receive the status signals and will produce the sequences of the control signals the control unit will decode the microinstructions into microoperations and will send it to the Data Unit.

The Data Unit works as a medium between the I$/$O interface and the Control Unit; The I$/$O is only connected to the Data Unit. The Control Unit does not have direct access to the I$/$O interface, it gets the I$/$O information from the Data Unit. The Control Unit will produce all the desired control signals which correspond to different microoperations that need to be executed using the status signals $($address bits, opcode, flags$)$ which are provided via the connection between the Control Unit and Data Unit.

Central Processing Unit As shown in the figure, the CPU consists of a control unit and a data unit.

The control unit produces sequences of control signals that correspond to the different microoperations that need to execute, such as register load, register increment, register clear, memory read, memory write, ALU operation selection, etc. These control signals are generated by using the status signals provided by the data unit. The status signals include the machine instruction bits $($composed of the opcode, indirect bit, and the address bits$),$ and status flag bits, such as Z$,$ I, N$,$ S$,$ FGI and FGO.

The control unit includes: $1)$ Control memory: $256$ x $222)$ Control address register $($CAR$)$: $8$ bits. $3)$ Subroutine register $($SBR$)$: $8$ bits. $4)$ Counter to build the timing circuit. $5)$ Decoders to decode microinstruction control word into microoperations. $6)$ Logic circuit to generate the control signals.While the data unit includes:

$1)$ Registers: $$ Address register $($AR$)$: $11$ bits. $$ Program counter $($PC$)$: $11$ bits. $$ Data register $($DR$)$: $16$ bits. $$ Accumulator $($AC$)$: $16$ bits. $$ Input register $($INPR$)$: $8$ bits. Its input is connected to the I$/$O interface module that is connected to the input device, and its output is connected to DR$(0-7).$

$$ Output register $($OUTR$)$: $8$ bits. DR$(0-7)$ and its output is connected to the I$/$O interface module that is connected to the output device.

$2)$ Flags $($all are$1$ bit in size$)$: $$ Zero flag $($Z$)$: Z $=1$ if AC $=0$; Z $=0$ otherwise. $$ Negative flag $($N$)$: N $=1$ if AC$(15)=1$; N $=0$ otherwise. $$ Indirect flag $($I$)$: I $=1$ if DR$(15)=1$; I $=0$ otherwise. $$ Input flag $($FGI$)$: FGI $=0$ if INPR is empty and ready to receive data from an input device. $$ Output flag $($FGO$)$: FGO $=1$ if OUTR is empty and ready to receive data from DR to be sent to an output device.

$$ Start$/$Stop flag $($S$)$: if S $=0$ stop execution of programs; otherwise allow execution. S is initialized to $1.$

$3)$ Arithmetic, logic, and shift unit: it is responsible for performing arithmetic, logic, and shift operations.

I$/$O Interface Module and Input$/$Output devices: The I$/$O interface module can be implemented using a buffer of size $4$ x $8.$ This means that it has $4$ registers each with $8$ bits. The I$/$O interface module can control the input$-$output data transfer operations by the shown control signals, such as input ready, output ready, insert, and delete.

The CPU is connected to the input and output devices via the I$/$O interface modules. The figure shows the data lines and control lines used in the connection.

Instruction Set and Detailed Architecture:

The Appendix includes the details of the instruction set and the architecture that needs to be designed and simulated. You can see that the instruction set is different from that presented in the textbook. Moreover, the computer hardware configuration is slightly different from Chapter $7$ as it has more registers $($such as INPR and OUTR$)$ and more flags $($such as S$,$ N$,$ FGI, FGO, etc.$).$

Computer Hardware Configuration