Design a $2-$bit alu accumalator that have $2$ inputs X$($X$1,$X$0)$ and Y$($Y$1,$Y$0)$ with one selection bit S used to select operation and one $2$ bit output $($F$1,$F$0),$ one bit output$($ Cout, Bout$)$ and two feedbacks D$0$ and D$1$

With $2$ operations

Operation $1$: Subtraction F$=$X$-$Y

Operation $2$: Add $2\text{'}$s complement of Y to X$,$ F$=$ X$+$ Y$\text{'}($Complemnt of Y$)+1$

What is truth table, k map, boolean operation, logic gates for the circuit, circuit design with $555$ timer and $32-1$ multiplexers for $($Cout$,$ F$1,$ F$0)$ and adding D$0,$ D$1$ registers

And how to connect the circuit and the circuit design

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