Design a $3-$bit decrementing counter. The counter registers will start at $000$ and in the next

clock rising edge, it will have a value of $111.$ After $111,$ the counter will have a value of $110$

at the next clock rising edge. Each register will have $D$ input, $R$ input, EN input and CLK

input. Each register will have a Q output. Assume that a reset signal is provided that you

connect to the $R$ input of the register and not needed anywhere else. Show the block

diagram with $3$ registers and the combinational logic needed to drive the D and EN inputs

of the $3$ registers. The EN input can be fixed to $1($D input is passed on to Q output every

clock rising edge$)$ or it can be driven by combinational logic. Show all work. Draw the circuit design with the registers