Design a 4-bit up-counter with a CE (count enable) and load control inputs and an additional output upper that outputs a 1 whenever the counter is within the upper half of the counter's range, 8 to 15, otherwise 0. Design the counter using MUXes and gates and D flip flops without any external control signal (e.g. reset or set). Model the circuit in Verilog HDL. Simulate your Verilog module. (25 Points)