Design a BCD to 7-segment decoder using Verilog behavioral modeling (Always block). One of the inputs to this circuit is the BCD number. The eight outputs are the various segments of the display (including the decimal point). For this design, modify your decoder to include the alpha characters A-F. You design should work as follows.

Exp 7: BCD to 7-Segment Decoder (Behavioral Model) Obiectives: - To design and implement a non-standard decoder using a behavioral model (Always block) - To see the ease at which extra features can be modeled using behavioral modeling Background: The design of a BCD-to-7-segment decoder is not considered one of the more challenging feats in digital design. This experiment adds some features to the previously designed decoder in an attempt to make a boring experiment slightly more exciting. The added features are not that amazing but there is a point. The general rule with HDLs is that if you can design something using a dataflow (RTL) model, they you should. If you have to put too much extra effort into designing a circuit using a dataflow (RTI.) model, strongly consider switching to a behavioral model. So for this experiment, you're basically going to re-implement the decoder in a previous experiment and include some added features. Assignment: Design a BCD to 7-segment decoder using Verilog behavioral modeling (Always block). One of the inputs to this circuit is the BCD number. The eight outputs are the various segments of the display (including the decimal point). For this design, modify your decoder to include the alpha characters A-F. You design should work as follows. - If BTN2 is pressed, no 7-segment display should beon. - BTN1 \& BTN0 determine which 7-segment display is actuated according to Table0.1. Table 0.1: Individual 7-segment display output specification