Design a binary integer multiply pipeline with ve s1:ages.The rst stage is for partial productgeneration.The last stage is a 36-bit tarrylookahead adder.The middle three stages are made of 16 carry-save adders (CSAs} of appropriate lengths.

(a) Prepare a schematic design of the ve-stage multiplypipeline.All linewidthsandinterstage connections must be shown.

(b) Determine the rnraximal clock rate of the pipeline if the stage delays are t| = F2 = t3 = t4= 9 ns. t5 = 4 ns,and the latch delay is 1 ns.

{c} What is the maximal throughput of this pipeline in terms of the number of 36-bit results generated per second?