Design a circuit that determines the magnitude of the difference D1D0 of two-bit numbers A1A0 and B1B0.; i.e. D1D0 = |A1A0 - B1B0|. Realize the CSOP expressions for the result D1D0 using MSI decoders or multiplexers and any additional SSI logic needed. Use as few MSI devices and as few additional SSI devices as possible. Using the schematic entry feature of Quartus II software, enter, compile, and simulate your design. Make sure the device assignment for the project is either Cyclone II or Cyclone IV E. Not all of the lpm functions are supported for all devices. Verify the correct operation of your circuit simulation, i.e. the simulation should match the function table from your design.

Quartus MSI Devices Many MSI device parts such as decoders and multiplexers can be found in the Quartus maxplus2 library. The maxplus2 library is a sub library of the others library, see Figure 1. For example, the 74138 and dec38 parts are 3 to 8 decoders. The 74151 and 74251 (3 state) are 8 to 1 multiplexers. The 161mux is a 16x1 multiplexer (Note 74150 and 74250 are 16x1 multiplexers but they not in the Quartus libraries). The 74154, 16dmux, and 16ndmux are all 4 to 16 decoders. Multiplexers and decoders of custom sizes can be created using the Quartus software megafunctions including the library of parameterized modules (LPM) functions. The LPM functions can be found in the megafunctions/gates library as shown in Figure 2. Multiplexers can be created using lpm_mux and decoders using lpm_decode. The devices inputs, outputs, and operation are specified via several menus. Make sure the device assignment for the project is either Cyclone II or Cyclone IV E. Not all of the lpm functions are supported for all devices. For the lpm_mux: First window- select a VHDL output file Second window - select the number of input lines for the mux (8 to 1 mux would have 8), keep each data input 1-bit wide, the appropriate number of selects will be generated, choose no for Do you want to pipeline the multiplexer Third window keep the defaults Fourth window keep the defaults, hit finish For the lpm_decode (Figure 3 shows the end result of creating a 3 to 8 decoder with enable and no pipelining) First window- select a VHDL output file Second window select the number of inputs (this is number of bits to decode, 3 to 8 decoder would have 3), you can choose to have an enable or not Third window choose which outputs to add (add all to get a standard sized decoder), keep the radix as decimal Fourth window choose no for Do you want to pipeline the function Fifth window keep the defaults Sixth window - keep the defaults, hit finish