Design a circuit that receives only clock_50 as the input clock and Key(0) as the power-up reset and outputs a periodic (or clock) signal, out_clock with a selectable frequency. The SW(1 downto 0) will be used to select the desired out_clock frequency as shown in the table below. Submit VHDL codes

Q3: Design a circuit that receives only "clock_50" as the input clock and "Key(0)" as the power-up reset and outputs a periodic (or clock) signal, "out_clock" with a selectable frequency. The SW(1 downto 0) will be used to select the desired "out_clock" frequency as shown in the table below. Submit VHDL codes (HW2Q3.vhd)