design a combinational-logic Address Decoder for a Microprocessor-based system. Your Decoder must generate XXXX _SEL_H signals for the following Memory or I/O Registers Devices:

1. a 256KBytes of RAM, (256K bytes) (Lower region of memory)
2. a 256Kbytes of ROM. (256K bytes) (Highest region of memory)

Besides these memory devices there will be a Universal Asynchronous Transmitter and Receiver (UART) having the following single-byte I/O Registers:

1. write-only TransmitDataBufferRegister (TDBR), ( 1 byte)
2. read-only ReceiveDataBufferRegister (RDBR), (1 byte)
3. read-only UARTStatusRegister(USTSR), (1 byte)
4. write-only UARTControlRegister (UCTLR). (1 byte)

Assume that the Microprocessor System has a 20-bit Address Bus (5 hex characters) and that the above Devices are located at the following Memory Address Space regions: (Note all addresses are given in hexadecimal but you will have to use a binary (per address line) representation in order to perform an accurate decoding.)

These Device are mapped-to (or located-at) the following regions in the 20-bit address space:

Device Name	Device Description	Start Address	Ending Address	Device Select Signal
RAM	Random Access Memory	00000	3FFFF	RAM_SEL_H
ROM	Read Only Memory (RD)	C0000	FFFFF	ROM_SEL_H
UART	UART Registers	BFFF0	BFFF3	(see below)
UART-TDBR	Transmit (WR)Data Register	BFFF0	BFFF0	UTDBR_SEL_H
UART-RDBR	Receive (RD) Data Register	BFFF1	BFFF1	URDBR_SEL_H
UART-STSR	Status (RD) Register	BFFF2	BFFF2	USTSR_SEL_H
UART-CTLR	Control (WR) Register	BFFF3	BFFF3	UCTLR_SEL_H

Signals coming from the microprocessor into the address decoder:

1. (A19-A00) - Address lines A_19 downto A_00 the most significant address lines is A19. When A19 line is high the address falls into the second half megabyte of the one megabyte address space, when A18 is high the address falls into the second quarter of the half megabyte indicated by A19, when A 18 is low the address falls into the first quarter of the half megabyte indicated by A19, etc...Note that because the RAM and ROM have a size of a quarter (256K) of megabyte, these two address lines should be sufficient to decode the RAM or ROM location (plus the other qualifying signals suchas (AS_H, WR_H, RD_H).
2. AS_H - Address Strobe asserted high. This signal is usually low but goes high when the address emitted by the microprocessor is valid and remains high till through-out the microprocessor read or write cycle.
3. RD_H Read cycle indicator when asserted high. This signal emitted by the microprocessor is usually low but is asserted to a high value when the microprocessor is performing a read cycle to any device mapped into its address space
4. WR_H -Write cycle indicator when asserted high. This signal emitted by the microprocessor is usually low but is asserted to a high value when the microprocessor is performing a write cycle to any device mapped into its address space
5. Note that your Decoder should contain seven combinational logic functions (one for each output) that use these input signals to determine when to generate each one of the seven XXXX_SEL_H output signals.

Project Evaluation Rubric(30 pts):

1. Address Decoder Block Diagram depicting all input and output signals (5pts)
2. VHDL Model of your Decoder ( 10 pts)
3. VHDL Test Bench Model of your Decoder (10)
4. Simulation Results Timing Diagram screen capture: (5)