Design a combinatorial circuit in Verilog with 8 active high request inputs Q0 through Q7, and 8 outputs A2-A0, AVALID, B2-B0, and BVALID, where the Q7 input has the highest priority, the "A" outputs identify the highest priority asserted input, and the "B" outputs identify the 2nd highest priority. Your deisgn may use discrete gates, decoders, and an 8-input priority encoder.

Priority encoder 17 16 I5 14 13 A2 A0 - 12 IDLE 10 Figure 7-11 Logic symbol for a generic 8-input priority encoder