Design a MUX-DEMUX with registered outputs:

Design will have a 4-to-1 MUX followed by a 1-to-8 DEMUX.

Use flip-flops for DEMUX outputs by instantiating DFF as in

COMPONENT DFF IS

PORT( D : IN STD_LOGIC;

CLOCK : IN STD_LOGIC;

Q : OUT STD_LOGIC );

END COMPONENT;