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Design a testbench in eda playground for the following verilog module such that waveform results can be viewed / / Moore - type Finite State
Design a testbench in eda playground for the following verilog module such that waveform results can be viewed
Mooretype Finite State Machine
For a traffic light controller
module trafficlightfsm
Inputs Traffic sensors for:
input wire TaAvenue
input wire TbBoulevard
outputs Traffic Lights for:
output reg : LaAvenue
output reg : Lb Boulevard
;
set up the state encodings
parameter Sb; state
parameter Sb; state
parameter Sb; state
parameter Sb; state
set up the current and next state registers
reg : state, next;
determine the outputs
always @ posedge clk or posedge rst begin
using this ifelse statement makes sure you take care of reset
if rst begin
state S; start at state
La b; Avenue light green
Lb b; boulevard light red
end else begin
state next;
start a case statement that sets the outputs based on current state
casestate
S: begin
La b; Avenue light green
Lb b; Boulevard light red
end
S: begin
La b; Avenue light yellow
Lb b; Boulevard light red
end
S: begin
La b; Avenue light red
Lb b; Boulevard light green
end
S: begin
La b; Avenue light red
Lb b; Boulevard light yellow
end
make sure to give a default when using case statements
for a traffic light, set all lights to red to prevent accidents
default: begin
La b; Avenue light red
Lb b; Boulevard light red
end
endcase
end
end
State transitions: move on to the next state
always statement: Ta and Tb are in the sensitivity list
because the next state are determined by these values
always @ Ta Tb begin
casestate
S: begin
if Ta if theres no traffic on Avenue,
next S; move to the next state
else otherwise
next S; stay in this state
end
S: begin
next S; traffic doesn't affect this state. Move on to the next state
end
S: begin
ifTb if no traffic on Boulevard
next S; move on to the next state
else otherwise
next S; stay in this state
end
S: begin
next S; traffic doesn't affect this state. Move on to the next state
end
handle the default case for this case statement
default: begin
next S;
end
endcase
end
endmodule
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