Design a Verilog data-flow module for a 4-bit by 4-bit binary adder?

Input: a3,a2,a1,a0, b3,b2,b1,b0, carryIn,

Output: s0,s1,s2,s3, carryOut

(Ex: input 1000 + 0101 + 1

Output 1110 + 0)

Addend Augend Carry out K 4-bit binary adder Zg Z4 Z2 Z Carry in