Design a VHDL module for each of the following circuits. Your solutions should include VHDL source code with comments. Assume positive clock edge trigger for all flip-flops. Use a text editor that will substitute spaces for tabs for all your VHDL code.

1. Sixteen Bit Up/Down Counter

Inputs: clock, reset, ud

Outputs: 16-bit counter value

Implement all 16-bits in a single VHDL process. The reset signal should synchronously reset the counter to zero. When ud = 1, the counter should increment on each clock cycle. When ud = 0, the counter should decrement on each clock cycle.