Design a VHDL module that implements the following Quiz Game functionality: There is a 2-bit vector output that indicates the winner of a round There are three contestant buttons. A contestant presses their button if they want to answer a question. If only a single button is pressed then the winner output will reflect the number of the button pressed (subject to the following conditions). . . .If more than one button is pressed then the unfair output should be active and winner is zero There is also an adjudicator's button. The adjudicator can press their button if they believe the question is unfair. In this case the unfair output should be active and the winner output should be zero (Yes I know this is a silly quiz game - it's just an example!) Implement this function using the ISE software and verify its operation on the hardware Winner Game Circuit Unfair Adjudicator Design a VHDL module that implements the following Quiz Game functionality: There is a 2-bit vector output that indicates the winner of a round There are three contestant buttons. A contestant presses their button if they want to answer a question. If only a single button is pressed then the winner output will reflect the number of the button pressed (subject to the following conditions). . . .If more than one button is pressed then the unfair output should be active and winner is zero There is also an adjudicator's button. The adjudicator can press their button if they believe the question is unfair. In this case the unfair output should be active and the winner output should be zero (Yes I know this is a silly quiz game - it's just an example!) Implement this function using the ISE software and verify its operation on the hardware Winner Game Circuit Unfair Adjudicator