Design and estimate the propagation delay of a 16-bit hybrid adder using a. Two CLA(8) modules b. Four CLA(4) modules c. Eight CLA(2) modules Can someone explain in detail this for me? Please don't copy and paste in an answer from another question, I've googled it already I've seen that answer it and doesn't make complete sense to me hence why I am posting this question. Looking for a different view of the same problem.