Design and implement a modified Verilog module to have it increment through one second intervals with improved accuracy. Do this by completing the module below. The BCD counting should use four signals, bcd3, bcd2, bcd1 and bcd0, representing the respective 10-, 1-, 0.1-, and 0.01-second columns on HEX3, HEX2, HEX1 and HEX0 displays. The pushbutton KEY[0] is an input that resets the counter to zero, when it goes from not pressed, KEY[0] = 1, to pressed, KEY[0] = 0. Choose the appropriate number of bits for the count variable to show the respective 10-, 1-, 0.1- and 0.01-second columns on HEX3, HEX2, HEX1 and HEX0 displays, within 5% error.

Lab 5 II A 4-digit BCD counter with HEX3 HEX2 HEX1 and HEX0 displaying decimal counting digits with approximately 10 1, 0.1, 0.01 second columns module Lab5II CLOCK 50 KEY HEX3 HEX2 HExi. HEX0 LEDG input CLOCK 50 input 13:0) KEY output 10:61 HEX3 HEX2 HEX1 HEX0 output reg [7:0] LEDG count reg reg 13:01 bcd0 bcd1 bcd2 bcd3 always e (posedge (CLOCK 50 begin LEDG count [7:0 count Count 1'bl; end always e (posedge CLOCK 50 if KEY begin bcd1 4'h0 bcd2 4 ho bca3 4' ho end. else if Count begin if (bcd0 4 'h begin bcd0 4 ho if bcdl begin bcd 1 4'h0 end else begin end end else begin bcd0 bcd0 1 lbl end end HEX3 displays the value of bcd3 bcd7seg digit bcd3 HEX3 HEX2 displays the value of bcd2 bcd7seg digit bcd2 HEX2 HEXl displays the value of bcdl bcd7seg digit bcd1 HEXl HEX0 displays the value of bcd0 bcd7seg digito (bca0, HEX0 endmodule The module bcd7 seg displays the bcd value on the specified 7-segment display module bcd7seg (bcd, display input [3:0] bucd; output [0:61 display reg [0 61 display always e bcd. bcd Case display 7' b0000001 4'h0 4'h1 display 7' b1001111; 4'h2 display 7 b0010010 4 h3 display 7 b0000110 display 7 b1001 100 4'h4 h5 display b0100 100 4'h6 display 7'bl 100000; 4 h7 display 7 b0001111 display 7 b0000000; display 7' b0001100 default display 7'bl 111111 endcase endmodule