Design and implementation of 8 bit serial/ parallel input serial output shift register using behavioral style of modelling.

I'm using 74LS166 8-BIT SHIFT REGISTERS IC.

http://www.esi.uclm.es/www/isanchez/apuntes/ci/74166.pdf

1.Is this IC has 9 input+clk Inhibit, clock, load and clear or reset and 1 output+ internal outputs??

2. code is correct??+ also write a testbench of code?

library ieee; use ieee.std_logic_1164.all;

entity siso is

generic ( n : integer := 4 );

port( clk: in std_logic; reset: in std_logic; enable: in std_logic; --enables shifting parallel_in: in std_logic_vector(7 downto 0); s_in: in std_logic; --serial input s_out: out std_logic --serial output ); end siso;

architecture behavioral of siso is signal temp_reg: std_logic_vector(7 downto 0) := (Others => '0'); begin process (clk) begin if (clk'event and clk='1') then if (enable ='1') then --shifting n number of bits for i in 0 to 7 loop s_out <= temp_reg(0); temp_reg <= s_in & temp_reg(7 downto 1); end loop; end if; end if; end process; end behavioral;