Design controller with the following specifications a Zero steady state error for unit step input. b - the output does not exhibit intersampling ripples should be 0.25 c - d- Steady state error for unit ramp Settling time must be minimum. Op (s) = Tal T=0.55. Sampling period is Design controller with the following specifications a Zero steady state error for unit step input. b - the output does not exhibit intersampling ripples should be 0.25 c - d- Steady state error for unit ramp Settling time must be minimum. Op (s) = Tal T=0.55. Sampling period is