Design FSM (Moore) that describe a serial comparator with n-bit unsigned numbers x and y as inputs. The FSM takes two bits x, and y at a time (every clock cycle). Assume the two bits are being fed in from MSB to LSB, e.g.x and y1 arrive at time unit 1 and xn2 and yn2 at time unit 2. The output of the FSM should be 00 for reset state . 01 if the two values are equal e 10 if x has a larger value 11 if y has a larger value You can assume that FSM has start state and can be reset to this state when new n-bit inputs (x &y) need to be evaluated Find the following 1. Draw the finite state diagram for the above-mentioned problem. 2. Write Verilog code for the finite state machine . Also write a test bench of FSM given in part 2. Design FSM (Moore) that describe a serial comparator with n-bit unsigned numbers x and y as inputs. The FSM takes two bits x, and y at a time (every clock cycle). Assume the two bits are being fed in from MSB to LSB, e.g.x and y1 arrive at time unit 1 and xn2 and yn2 at time unit 2. The output of the FSM should be 00 for reset state . 01 if the two values are equal e 10 if x has a larger value 11 if y has a larger value You can assume that FSM has start state and can be reset to this state when new n-bit inputs (x &y) need to be evaluated Find the following 1. Draw the finite state diagram for the above-mentioned problem. 2. Write Verilog code for the finite state machine . Also write a test bench of FSM given in part 2