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design in Verilog a leading one detector given an input number a, compute the index of the highest one bit bits in a are numbers
design in Verilog a leading one detector
given an input number a,
compute the index of the highest one bit
bits in a are numbers from 0 to 10, with a[0] being the least significant bit
if the input is zero, then the output should be 0, for instance: 01011011 -> 6
format:
module leadingone
(
input logic [10:0] a,
output logic [3:0] bnum
);
[insert code here]
endmodule // leadingone
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