Design the PREP benchmark 9 shown in Fig. 2a using Verilog. The design is a memory decoder common in microprocessor systems. The addresses are decoded only when the address strobe as is active. Addresses that fall outside the decoder activate a bus error be signal. The design has a 16-bit input a [15..0], an asynchronous active-low reset rst and all flip-flops are positive- edge triggered via clk. The following table summarizes the behavior (X=don't care): rst as clk a[15...0) (hex) be X 0 1 X 0 1 1 0 1 0 0 be 0 0 0 1 q[7...0] (binary) 00000000 00000000 q[7...0] 00000001 00000010 00000100 00001000 00010000 00100000 X X X FFFF to F000 EFFF to E800 E7FF to E400 E3FF to E300 E2FF to E2CO E2BF to E2BO 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1. E2AF to E2AC E2AB E2AA to 0000 01000000 10000000 00000000 0 0 1 Design the PREP benchmark 9 shown in Fig. 2a using Verilog. The design is a memory decoder common in microprocessor systems. The addresses are decoded only when the address strobe as is active. Addresses that fall outside the decoder activate a bus error be signal. The design has a 16-bit input a [15..0], an asynchronous active-low reset rst and all flip-flops are positive- edge triggered via clk. The following table summarizes the behavior (X=don't care): rst as clk a[15...0) (hex) be X 0 1 X 0 1 1 0 1 0 0 be 0 0 0 1 q[7...0] (binary) 00000000 00000000 q[7...0] 00000001 00000010 00000100 00001000 00010000 00100000 X X X FFFF to F000 EFFF to E800 E7FF to E400 E3FF to E300 E2FF to E2CO E2BF to E2BO 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1. E2AF to E2AC E2AB E2AA to 0000 01000000 10000000 00000000 0 0 1