Design the Shift Counter that is used in the data path logic of the SRC. The counter must take in a 3-bit binary number, then, starting at that number must count down to 00000, in steps of 1 for each clock, as long as the DECREMENT input is 1. If the DECREMENT input is 0, the output must stay in its current state, wherever it is. Ignore the LOAD input line. Notice also that we have changed the count from a 5-bit number to a 3-bit number to simplify the state transition diagram and design. Draw the state transition diagram, the state table, the state table with state assignments, the truth table and implementation of the circuit. please explain your answers