Design your Verilog FIR code and test the coherence of the data and find the latency $($in terms of clock cycles$)$ for each design. The focus for this assignment is to get correct data alignment and coherence. Comment on the latency and alignment of data in your simulation results. In this question we will add registers at the outputs of all the multipliers. This way multiplication will occur in one clock cycle and then addition will occur in the following clock cycle. Report the latency and the Hardware usage in this case. Include all Verilog code including the test bench, explanations, and simulation results.