1. Determine the amount of delay (TD) needed to generate a PWM with a period of 0.7ms. Then determine the size of the counter (n) and the constant Delay.
2. Write the Verilog description of the pulse width modulator using only one module.
3. Simulate the PWM using a test bench to verify its operation.

PWM Generator: Delay (constant) PW PW Comparator PWM Delay counter n Period Counter8/ Enable 8-bit Load The delay counter is reloaded with Delay upon reaching zero. It counts from Delay down to zero. The signal Enable is asserted only when the delay counter is zero. The signal PWM is high when the period counter is smaller than PW PW PWM 0 255 0 PWM Generator: Delay (constant) PW PW Comparator PWM Delay counter n Period Counter8/ Enable 8-bit Load The delay counter is reloaded with Delay upon reaching zero. It counts from Delay down to zero. The signal Enable is asserted only when the delay counter is zero. The signal PWM is high when the period counter is smaller than PW PW PWM 0 255 0