1. Determine the clock cycle at which each of the instructions in the sequence given below would be completed, assuming the 5-stage pipeline without forwarding covered in class, and numbering the clock cycle at which the first of the instructions is fetched as clock cycle Assume that if one instruction reads a register during the same clock cycle as another instruction is writing it, the new value will be read. Do not reorder the instructions. Instructions are fetched and executed exactly in the order given below, with the pipeline stalling if necessary.

addi $s2, $s2,1

add $s6,$s1,$s3

add $s1,$s2,$s3

lw $s5,0($s1)

lw $t1,0($s5)