Digital circuit design & System Verilog

In mathematics, linear programming specifically refers to the optimization problem where both the objective function and constraints are linear. This exam requires everyone to complete an integer linear programming circuit to find the optimal integer solution that satisfies the constraints.

Any linear programming problem can be expressed in the following form:

The circuit designed in this question computes a two$-$dimensional linear programming problem with six constraints using variables $1$ and $2,$ and finds the maximum value of the objective function where $1$ and $2$ are both integers. Thus, in the above expression $(1),$ represents the coefficients of the objective function; A is a $6\backslash$times $2$ matrix, where the first and second rows represent the coefficients of the $1$ and $2$ variables for the constraints.

For example, consider the following linear programming problem:

Objective function:

Constraints:

In this example, applying expression $(1),=[13]$

The circular points in the graph represent integer solutions that satisfy the constraints. The objective function has a maximum value of $12$ at x $=.$

In this question, each input from the pattern includes four sets similar to the example provided. These will define a rectangular region of constraints on the two$-$dimensional coordinate system. The length and width of this rectangular region will not exceed $15,$ and the upper and lower bounds of $1$ and $2$ will not exceed $\backslash$pm $31.$

All intersection of constraints provided by the pattern will have a non$-$empty solution set, i$.$e$.,$ there will always be a solution.

Inputs and Outputs:

Each input from the pattern will raise in$\_$valid and provide values to in$\_$a$1,$ in$\_$a$2,$ in$\_$b for $7$ cycles. In the first cycle, in$\_$a$1$ and in$\_$a$2$ will provide the coefficients $1$ and $2$ of the objective function, while in$\_$b will be $0.$ In the subsequent cycles $(2$ to $7),$ in$\_$a$1$ will input the coefficients of $1$ for the six constraints, in$\_$a$2$ will input the coefficients of $2$ for the six constraints, and in$\_$b will input b$.$

Note that the order of inputting the six constraints in cycles $2$ to $7$ is random. For example, the order of constraints input might vary as shown in different figures but will still represent the same linear programming problem.

When outputting the result, out$\_$valid will be raised, and out$\_$max$\_$value will output the maximum value of the objective function for the solution that satisfies the constraints and where $1$ and $2$ are integers, lasting for $1$ cycle.

Hint:

Since the question seeks integer solutions for $1$ and $2,$ and four constraints frame a rectangle not exceeding $15$x$15,$ you can enumerate all integer coordinates within the rectangular range and check the remaining two constraints to find the optimal solution that satisfies the conditions.

Specifications:

$1.$ Top module name: LP $($File name: LP$.$sv$)$

$2.$ After asynchronous negative$-$edge reset, all output signals must be reset to zero.

$3.$ Outputs must be provided within $300$ cycles after the end of input.

$4.$ Output should only be provided for $1$ cycle, neither more nor less.

$5.$ The next input will be sent $1$ to $4$ cycles after out$\_$valid is pulled down.

$6.$ The $02\_$SYN result cannot have errors and must not have any latches.

$7.$ The slack in the timing report must be non$-$negative, and the result must be Met.

$8.$ There should be no timing violations in the gate$-$level simulation.

$9.$ Clock period is $10$ ns$.$

$10.$ Input delay $=0\mathrm{.}5*$ clock period; Output delay $=0\mathrm{.}5*$ clock period

$11.$ Do not use $*$error$*,*$latch$*,*$congratulation$*,$ or $*$fail$*$ as logic$/$wire$/$reg$/$submodule$/$parameter names, otherwise, the demo result will be fail.

Note: $*$ represents any symbol before or after the word, for example: error$\_$test is prohibited.

Please write your system Verilog code in the $$logic declaration$$ and $$your design$$ block in the below picture.