following functionality: 1) On startup we look at detecting the sequence 001 first. 2) After the leading sequence (001) is first detected we ignore subsequent instances of 001's and look to detect the sequence 111 (but without overlap with the previously detected sequence 001). 3) After a sequence 111 is detected we ignore subsequent instances of 111's and look again to detect the sequence 001. The process continues alternating between the detection of one sequence and then the other. X 2 Design a FSM that has one input bit stream X and one output Z, with the 4) The timing trace shown below depicts a possible example, using Moore (you can also use Mealy), with several events in order to clarify the prescribed functionality for this FSM. 5) Discuss any timing problem that you think your design solution may have, and give possible alternatives. If possible, provide alternative design solutions stating any trade-offs among them. 6) 7) Use LogiSim to verify, and demonstrate to the instructor, that your design works as intended. 10 0 100 1 0 0 1 0 0 00 10000 10000... 1 0 01000 01 0 4. 1 0 0 1 0 0 0 1 0 0 0 1 Design Constraints: (Note: Every time you cannot meet one of the constraints you may lose a few points.) 1. Do not use more than 3 Flip-Flops of any type. 2. Try to minimize the discrete gate count at the combinational logic stages. State what you did in order minimize the gate count. 3. The system can be a single system or use any number of subsystems (for example one subsystem for each sequence). You may use more Flip Flops, if needed, when providing extra alternative design solutions. In such case discuss pros and cons. 5. No sequence overlap is allowed for this detector. X0. CKL reset @ ****** SeqDetMoore 001_111. X CK reset: ON OZ Output 000, Present State