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General Description: You are to create an 8-to-1 MUX using 7 instances of the Xilinx 2-to-1 MUX module named (M2_1) in the library of parts. You design will have eight data inputs, one bit each (d7d0). There will be one output, also being 1-bit (y). The MUX is to be created using ONLY 2-to-1 MUXs, having two data inputs (one bit each) and one output, also being 1-bit. The purpose of this lab is to use structural modeling techniques with the schematic editor. The unconnected structure of the 8-to-1 MUX is shown in the diagram below:

Based on the information and diagram, provide verilog testbench code

Notes: the select lines to the individual 2-to-1 MUX's must be connected to the appropriate select lines that are inputs to the 8-to-1 MUX M2 1 DO D1 SO M2 1 DO D1 SO M2 1 M2 1 DO D1 SO DO D1 SO M2 1 M2 1 DO D1 SO DO D1 SO M2 1 DO D1 SO Notes: the select lines to the individual 2-to-1 MUX's must be connected to the appropriate select lines that are inputs to the 8-to-1 MUX M2 1 DO D1 SO M2 1 DO D1 SO M2 1 M2 1 DO D1 SO DO D1 SO M2 1 M2 1 DO D1 SO DO D1 SO M2 1 DO D1 SO