Draw a stick diagram for a complex-gate of uninterrupted active regions implementing Y = (X1X2 +X3 +X4)'. Adopting the minimum possible active width that can accommodate one contact, estimate the MOSFET drain and source areas and perimeters as needed in a transient analysis, and prepare the corresponding Spice netlist with a 10-fF external capacitance attached to the output. Next, inspect the electrical schematic to decide which input variable stepping up from logic-0 to logic-I will result in the longest high-to-low propagation delay. Finally, define and run a transient analysis consistent with your decision, and read TPHL