DRAW THE CACHE MEMORY DIAGRAM AS ASKED IN THE QUESTIONS WILLING TO GIVE MASSIVE THUMBS UP :D

1. Design a cache memory with a size of 256kB. Provide the following information in your answer (show all your work): a. Specify your design choices: What is size of each block? b. Specify your design choices: What is size of each word? c. Specify your design choices: What type of set association you are implementing? d. Specify your design choices: How many groups all the sets are divided? e. Specify your design choices: What happens on read hit and read miss? f. Specify your design choices: What happens on write hit and write miss? g. What is the size of the physical address from CPU (according to you design)? h. How many sets and blocks are there in the cache (according to you design)? i. Justify the size of cache (should be 256kB ) again from your design choices. j. How many words per group? How many bits needed to index the number of words per group? k. Draw a block diagram for your cache design showing the design choices, the cache operation and all the routing. Mention the key points of overall cache operation from the diagram. You can follow the way example block diagram is drawn as follows (please see the next page)